1. Field of the Invention
This invention relates to digital electronic circuits and in particular to transparent latches.
2. Discussion of Prior Art
A transparent latch is a digital function which has one signal input (D), one signal output (Q) and a control input C.
The control input is used to select one of two modes of operation. In a first mode, the output (Q) changes to follow any changes in the input (D). In the second mode, the output remains set to the input condition existing at the point of mode change.
The above function can be represented by either of the following Boolean expression: EQU Q=D.C+Q.C
when the first mode is such that C is true: or by its dual: EQU Q=D.C+Q.C
when the first mode is such that C is false
The above expressions can be realised in a number of known ways, one of which is shown in FIG. 1. The transparent latch of FIG. 1 and other known versions are described in Texas instruments Data Book Vol I 1989.
The truth table (where H=true and L=false) for the circuit of FIG. 1 is as below:
D C Q H H H L H L H L Q.sub.0 L L Q.sub.0
i.e. when the control input (C) is high, the latch is transparent, with Q following D, and when the control input (C) is low the output Q remains latched at its previous level Q.sub.o.
The circuit of FIG. 1 comprises first and second AND gates 1, 2 whose outputs are fed to an OR gate 3 which provides the final output Q. Inputs D and C are fed to the first AND gate 1 while the second AND gate 2 receives the final output Q and C as inputs. C is derived from C by means of an inverter/NOT gate 4.
As can readily be seen from inspection of FIG. 1, the OR gate 3 makes the choice between D or the existing value of Q, the choice being controlled by the current state of C, this being the principle of operation of all known transparent latches.
It will also be noted that for correct operation of the circuit under all possible conditions, particular care must be taken in the layout of the latch so that propagation delays through gates and interconnecting wires and are accounted for. This constraint on the design layout is inherent in all known latches. If these propagation delays are not properly accounted for then a failure condition can occur. For example, when the control input (C) is high and D is high, the input to gate 3 from gate 1 will be high and the input to gate 3 from gate 2 will be low. If the control input (C) is now taken low and the input to gate 3 from gate 1 goes low before the input to gate 3 from gate 2 goes high, the output (Q) can be erroneously latched low.